1. Field of the Invention
The invention relates to the manufacture of electronic devices. More particularly, the invention relates to the fabrication of capacitors within a dynamic random access memory (DRAM) device.
2. Description of the Related Art
Capacitors are used in electronic devices such as integrated circuits (ICs) for storing electrical charge. In ICs such as dynamic random access memory (DRAM), capacitors are used for storage in the memory cells.
Typically, capacitors formed in ICs include a bottom electrode (storage node) made of, e.g., polycrystalline silicon (polysilicon) or hemispherical grain polysilicon (HSG), a dielectric layer made of, e.g., tantalum pentoxide (Ta.sub.2 O.sub.5) and barium strontium titantate (BaSrTiO.sub.3 or BST), and an upper electrode (cell plate) made of, e.g., titanium nitride (TiN), titanium (Ti), tungsten (W), platinum (Pt), polysilicon or other semiconductor conducting materials.
In any fabrication process, simplicity and efficiency is an advantage. A fabrication process that achieves the same or better quality product or higher yield with the same cost of materials while using fewer steps is advantageous, especially if elimination of fabrication steps reduces labor costs and the need for expensive manufacturing equipment. Also, a fabrication process that achieves a better quality product or higher yield but at a slightly higher cost and/or increased number of fabrication steps may nonetheless be advantageous in terms of overall process efficiency.
IC capacitor fabrication processes are exist. For example, Radosevich et al., in U.S. Pat. No. 5,576,240, discloses a method for fabricating a metal-to-metal (MOM) capacitor. The method improves processing flexibility and the quality of the produced product while proposing to reduce or maintain the existing costs of conventional processes. Also, Patterson et al., in U.S. Pat. No. 5,065,220, discloses a metal-to-polysilicon capacitor and its method for making in which the dielectric layer is deposited via low-pressure chemical vapor deposition (LPCVD).
However, the dielectric layer of capacitors formed in ICs typically is a high K dielectric material that does not respond well to conventional etching techniques. Therefore, it would be advantageous for fabrication processes to facilitate the use of processes other than etching, such as chemical-mechanical polishing (CMP) and other planarization techniques, particularly with respect to the formation of the dielectric layer of the capacitor. CMP also is advantageous in that it contributes to the maintenance of the planarization across the semiconductor topography. Also, conventional IC capacitor fabrication processes typically require changing process parameters of transistors and other electronic elements during the manufacture of the semiconductor body.
Therefore, it would be advantageous to have an IC capacitor fabrication process that is more compatible with the existing fabrication processes of other IC devices within the semiconductor device.